SM844256 10 gigabit ethernet and sonet, 6 output, ultra-low jitter lvds frequency synthesizer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com july 2010 m9999-072110-b general description the SM844256 provides a low-noise timing solution for high speed, high accuracy sy nthesis of clock signals. common applications include sonet, gigabit ethernet, 10 gigabit ethernet, and similar networking standards. it includes a power reduction methodology, along with a patented rotarywave tm architecture that provides a very stable clock with very low noise. power supplies of either 3.3v or 2.5v are supported, with superior jitter and phase noise performance. the device synthesizes different low noise lvds output frequencies such as 125mhz, 156.25mhz, 312.5mhz, and 625mhz for ethernet applications; 77.76mhz , 155.52mhz, 311.04mhz, and 622.08mhz for sonet applications. the crystal reference frequencies used include 25mhz and 19.44mhz for ethernet and sonet applications, respectively. the SM844256 is an excellent replacement for idt femto- clocks, with improved accuracy, power consumption, waveform integrity, and jitter. data sheets and support documentation can be found on micrel?s web site at: www.micrel.com . features ? generates six lvds outputs ? 2.5v or 3.3v operating range ? typical phase jitter @ 125mhz (1.875mhz to 20mhz): 80 fs (typical) @ 3.3v ? 75mhz to 625mhz output frequencies ? industrial temperature range ? green, rohs, and pfos compliant ? available in 24-pin tssop epad ? operating supply modes: core/output 3.3v/3.3v, 3.3v/2.5v, 2.5v/2.5v applications ? sonet ? gigabit ethernet ? 10-gigabit ethernet ? infiniband ________________________________________________________________________________________________________________________ block diagram
micrel, inc. SM844256 july 2010 2 m9999-072110-b ordering information (1, 2) part number marking shipping junction temperature range package SM844256ka 844256 tube, tape & reel ?40 to +85c 24-pin tssop epad notes: 1. devices are green, rohs, and pfos compliant. 2. lead finish is 100% matte tin. pin configuration 24-pin tssop epad (top view)
micrel, inc. SM844256 july 2010 3 m9999-072110-b pin description pin number pin name pin type pin level pin function 1, 2 v ddo pwr 2.5v or 3.3v power supply 3, 4 /q2, q2 o, (dif) lvds differential clock output 5, 6 /q1, q1 o, (dif) lvds differential clock output 7, 8 /q0, q0 o, (dif) lvds differential clock output 9 pll_bypass i, (se) lvcmos pull-up 45k, single-ended input select pin. logic (0) = pll output logic (1) = xtal reference 10 v dda pwr analog 3.3v or 2.5v power supply 11 v dd pwr 3.3v or 2.5v power supply 12 fb_sel i, (se) lvcmos pull-down 45k, single-ended input select pin 13 xtal_in i, (se) 12pf crystal crystal reference input, no load caps needed. 14 xtal_out o, (se) 12pf crystal crystal reference output, no load caps needed. 15 n_sel0 i, (se) lvcmos pull-up 45k, single-ended input select pin 16, 17 gnd pwr ground 18 n_sel1 i, (se) lvcmos pull-up 45k, single-ended input select pin 19, 20 /q5, q5 o, (dif) lvds differential clock output 21, 22 /q4, q4 o, (dif) lvds differential clock output 23, 24 /q3, q3 o, (dif) lvds differential clock output input and output frequency table x tal (mhz) fb_sel n_sel1 n_sel0 outputs (mhz) application 24 0 0 0 600 - 24 0 0 1 300 - 24 0 1 0 150 sas/sata 24 0 1 1 120 - 25 0 0 0 625 10 gigabit ethernet 25 0 0 1 312.50 10 gigabit ethernet 25 0 1 0 156.25 10 gigabit ethernet 25 0 1 1 125 gigabit ethernet/infiniband/pci/pci- e/pci-x 18.75 1 0 0 600 - 18.75 1 0 1 300 - 18.75 1 1 0 150 sas/sata 18.75 1 1 1 75 sas/sata 19.44 1 0 0 622.08 10 gigabit ethernet/sonet 19.44 1 0 1 311.04 sonet 19.44 1 1 0 155.52 sonet 19.44 1 1 1 77.76 sonet 19.53125 1 0 0 625 10 gigabit ethernet 19.53125 1 0 1 312.5 10 gigabit ethernet 19.53125 1 1 0 156.25 10 gigabit ethernet 19.53125 1 1 1 78.125 10 gigabit ethernet
micrel, inc. SM844256 july 2010 4 m9999-072110-b absolute maximum ratings (1) supply voltage (v dda , v dd , v ddo )................................+4.6v input voltage (v in )?????????-0.50v to v dd +0.5v lvds output current (i out )?????????? 10ma lead temperature (solde ring, 20sec .)....................... 260c case temper ature ..................................................... 115c storage temperature (t s ) ..........................-65c to +150c operating ratings (2) supply voltage (v ddo ) .......................... +2.375v to +3.465v supply voltage (v dd, v dda ).................... +2.375v to +3.465v ambient temperature (t a ) .......................... ?40c to +85c junction thermal resistance (3) tssop ( ja ).......................................................32 c/w dc electrical characteristics (4) v dda = v dd = 3.3v 5% or 2.5v 5%, v ddo = 2.5v 5%, t a = ?40c to +85c, unless noted. symbol parameter condition min typ max units v ddo 2.5v operating voltage 2.375 2.5 2.6 25 v v dda ,v dd 3.3v operating voltage 2.375 3.3 3.465 v f out = 156.25 mhz 55 tbd ma i dda analog supply range f out = 625.00 mhz 56 f out = 156.25 mhz 13 tbd ma i dd core supply current f out = 625.00 mhz 13 f out = 156.25 mhz 195 tbd ma i ddo i/o supply range f out = 625.00 mhz 200 v dda = v dd = v ddo = 3.3v 5%, t a = ?40c to +85c, unless noted. symbol parameter condition min typ max units v dda , v dd , v ddo 3.3v operating volt age 3.135 3.3 3.465 v f out = 156.25 mhz 55 65 ma i dda analog supply range f out = 625.00 mhz 56 f out = 156.25 mhz 13 17 ma i dd core supply current f out = 625.00 mhz 13 f out = 156.25 mhz 195 234 ma i ddo i/o supply range f out = 625.00 mhz 200 notes: 1. permanent device damage may occur if absolute maximum rati ngs are exceeded. this is a stress rating only and functional ope ration is not implied at conditions other than those detailed in the operational sections of this data shee t. exposure to absolute maximum rating con ditions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the pc b. 4. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establish ed.
micrel, inc. SM844256 july 2010 5 m9999-072110-b lvds dc electrical characteristics (5, 6, 7) v dda = v dd = 3.3v 5% or 2.5v 5%, v ddo = 2.5v or 3.3v 5%, t a = ?40c to +85c, unless noted. symbol parameter condition min typ max units v od differential output voltage figure 1 275 350 475 mv v od v od magnitude change 40 mv v os offset voltage 1.15 1.25 1.50 v v os v os magnitude change 50 mv lvcmos dc electrical characteristics (6) v dda = v dd = 3.3v 5% or 2.5v 5%, v ddo = 2.5v or 3.3v 5%, t a = ?40c to +85c, unless noted. symbol parameter condition min typ max units v ih input high voltage 2 v dd +0.3 v v il input low voltage -0.3 0.8 v i ih input high current (fb_sel) v dd = v in = 3.465v 150 a i ih input high current (pll_bypass), (n_sel0), (nsel1) v dd = v in = 3.465v 5 a i il input low current (fb_sel) v dd = 3.465v, v in = 0v -5 a i il input low current (pll_bypass), (n_sel0), (nsel1) v dd = 3.465v, v in = 0v -150 a ac electrical characteristics (8) v dda = v dd = 3.3v 5% or 2.5v 5%, v ddo = 2.5v or 3.3v 5%, t a = ?40c to +85c, unless noted. symbol parameter condition min typ max units f out output frequency refer to frequency table 75 625 mhz t jit ( ? ) rms phase jitter (random) 125mhz, integration range: (1.875mhz ? 20mhz) 80 fs t skew output-to-output skew note 9 65 ps t r /t f lvds output rise/fall time 20% ? 80% 100 160 300 ps odc output duty cycle 45 50 55 % t lock pll lock time 20 ms notes: 5. see figure 4 for load test circuit example. 6. the circuit is designed to meet the dc specifications shown in the above table(s) after thermal equilibrium has been establ ished. 7. outputs terminated 100 ? between q and /q. all unused outputs must be terminated. 8. the circuit is designed to meet the ac specifications shown in the above tabl e(s) after thermal equilibrium has been establ ished. 9. defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the output different ial crossing points.
micrel, inc. SM844256 july 2010 6 m9999-072110-b phase noise plot: 125mhz @ 3.3v figure 1. duty cycle timing figure 2. all outputs rise/fall time
micrel, inc. SM844256 july 2010 7 m9999-072110-b figure 3. rms phase noise/jitter figure 4. lvds output load and test circuit figure 5. crystal input interface
micrel, inc. SM844256 july 2010 8 m9999-072110-b package information 24-pin epad tssop micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in pers onal injury. life support devices or system s are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significan t injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2010 micrel, incorporated.
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